CMOS integrated circuits make extensive use of current sources; and, depending on required performance, particular circuit arrangements may be used the ensuring a good degree of stability with respect to specific parameters (temperature, supply voltage, technological variations, etc.). The following description takes into consideration a current source which, as far as possible, is independent of supply voltage, even when the supply voltage varies between 2.7 and 7-8 V. Of the various arrangements currently proposed, the most suitable for this purpose is shown in FIG. 1.
In detail, the current source in FIG. 1 comprises a current mirror circuit 1 formed by two P-channel transistors 2, 3 with a given width/length ratio W/L. Transistor 2 is diode-connected and presents the source terminal connected to the source terminal of transistor 3. The two source terminals are connected to supply V.sub.DD via a P-channel transistor 4 with a control terminal defining an input node 5 supplied with an inverted enabling signal CEN. The drain terminal of transistor 2 (defining node 6) is connected to the drain terminal of an N-channel transistor 7, the source terminal of which is grounded via a resistor 8, and the gate terminal of which is connected to the gate terminal of a further N-channel transistor 9, the source terminal of which is grounded, and the drain terminal of which is short-circuited to the gate terminal and connected to the drain terminal of transistor 3. A filtering capacitor 10 is connected between node 6 and ground, and likewise a native (low-threshold) N-channel boost transistor 11, the gate terminal of which defines an input node 12 supplied with the CEN signal. A P-channel transistor 15, similar to transistor 3, presents the gate terminal connected to node 6, the source terminal connected to supply V.sub.DD, and the drain terminal of which defines an output 16 supplied with a predetermined current I. Though no shown, node 6 may be connected to the gate terminals of additional transistors, similar to 15, if a number of current sources are required for the same device.
The relative dimensions of transistors 2 and 3 determine the ratio of the currents supplied respectively to transistors 7 and 9. For example, if (W/L).sub.3 is the dimensional parameter (width/length ratio) of transistor 3, and (W/L).sub.2 the dimensional parameter of transistor 2, and if (W/L).sub. =2(W/L).sub.2 : I.sub.3 =2I.sub.2, where I.sub.3 is the current through transistor 3 (which determines the output current I of the source), and I.sub.2 the current through transistor 2.
If transistors 7 and 9 present the same dimensions, the ratio of the currents flowing through them only remains the same as that set by transistors 2 and 3 if the respective gate-source voltage drops Vgs differ. In the above case, it is necessary that Vgs7&lt;Vgs9, where Vgs7 is the voltage drop between the gate and source terminals of transistor 7, and Vgs9 that of transistor 9.
The current I.sub.r through resistor 8, with a resistance R8 and a voltage drop V.sub.8, is therefore given by the following equation: EQU I.sub.r =V.sub.8 /R8=(Vgs9-Vgs7)/R8
As, roughly speaking, the gate-source voltage drops of transistors 7 and 9 depend solely on thee threshold voltage V.sub.T of the transistors and the current flowing through them, hence on I.sub.r, the latter is independent of supply voltage V.sub.DD.
In actual fact, however, a secondary effect exists, due to the output resistance of transistors 7, 9, which is not infinite and which results in a dependence of current I.sub.r on the drain-source voltage drop Vds of the transistors. In fact, due to transistors 2 and 9 being diode-connected, Vds2=Vgs2 and Vds9=Vgs9, which means Vds2 and Vds9 vary little alongside a variation in supply voltage. On the other hand: EQU Vds7+Vds2+V.sub.* =V.sub.DD
so that any variation in supply voltage must be absorbed by the drain-source voltage drop of transistor 7.
Since: EQU R.sub.R =K1/2*(W/L).sub.7 *(Vgs7-V.sub.T).sup.2 +Vd7/Ro7 (1)
where K1 is a constant depending on fabrication technology, (W/L).sub.7 is the dimensional parameter of transistor 7, and Ro7 is the output resistance of transistor 7 (see, for example, formula 9.2.11, page 441, of "Device Electronics for Integrated Circuits," second edition, by Richard S. Muller and Theodore I. Kamins, defining K*.lambda.*(V.sub.G -V.sub.T).sup.2 /2=1/Ro7), and since Ro7 is not of infinite value, the current through resistor 8 (and which is mirrored in the desired ratio into transistors 3 and 15) thus depends on the drain-source voltage drop of transistor 7 and hence on supply voltage V.sub.DD.
To solve this problem, several variations have been proposed using a number of transistors connected in series with transistors 7 and 9 to increase the equivalent output resistance of the transistors and so reduce the dependence of reference current I.sub.r on the drain-source voltage drop. Such solutions, however, fail to operate at low supply voltage V.sub.DD values, in that, to be turned on, a pile of n transistors in series requires a supply voltage of over n*V.sub.T, where VV.sub.T .about.0.6 V.
It is an object of the present invention to provide a current source which is substantially independent of supply voltage.